The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Conventional memory devices are typically configured so that during any given clock cycle only a single memory operation, such as a read operation, can be performed at a particular block of memory. In the context of some networking or switching applications, various data that is used for packet processing, for example control tables, forwarding tables and the like, are shared among various switching devices or switching cores of a single device. These multiple devices and cores together offer the ability to switch among a large number of ports. However, limitations on the ability of the multiple devices and cores to speedily access data stored in a shared memory can result in a reduction of switching capabilities. Alternatively, providing each device with its own memory device can be expensive both in terms of the direct cost of additional memory as well as in terms of resources required to the different memories synchronized.